In a static random access memory (SRAM), a data bit read from or written into a memory cell is typically represented as a differential voltage between a bit line pair that is coupled to the memory cell. Multiple memory cells are coupled to one bit line pair. During a write cycle of the memory, the data bit is driven onto the bit line pair as a differential voltage. The differential voltage is large enough to overwrite an existing value in the selected memory cell. When a read cycle occurs, the selected memory cell places a data bit stored within the selected memory cell onto the bit line pair as a relatively small differential voltage.
Before a read cycle can occur, the differential voltage that exists on the bit line pair must be reduced to a level low enough so that the data is not erroneously written into a memory cell during the read cycle. The differential voltage must be reduced quickly at the end of the write cycle so that the read cycle is not unnecessarily extended. This process is called write recovery. Write recovery is typically achieved by using circuits known as bit line loads.
A write cycle is typically initiated when an external write enable signal is asserted, an address is provided to the memory to select the memory cell to be written into, and data is provided to data input circuits. The bit line loads and write driver circuitry are controlled by the write enable signal to write data into the selected memory cell. The application of the address, data signal, and write enable signal must be timed very carefully to ensure that the correct data is written into the correct memory cell. There are write timing margins which must be observed to ensure reliable memory operation. Delay circuits, which provide a fixed amount of delay, are often used to ensure that the memory operates within the timing margins. However, deviations in the manufacturing process, power supply variations, and temperature variations may cause a race condition, where the write cycle may occur too fast, and a previously decoded memory array location may be inadvertently written into. Also, changes in the clock frequency can result in operation of the memory outside of the specified timing margins. In addition, deviations in process parameters and operating conditions can result in reduced yield during fabrication.